Yichuan Wang
Bio 
I am an incoming PhD student at UC Berkeley in SkyLab and the last-year undergraduate student in the ACM honor class of Shanghai Jiaotong University, majoring in computer science and technology. I am interested in machine learning systems and high-performance computing systems (to be more detailed maybe distributed systems for large ML model training, and develop tailored abstractions for unique ML computational patterns to achieve higher performance).
Currently, I am also collaborating with Prof.Jinyang Li in NYU on a project related to scale up GNN training. In SJTU, I am supervised by Prof. Quan Chen at EPCC.
I like to communicate with different people, so you can feel free to contact me via email wechat:15858459091 or yichuanwang0324 or twitter If you are willing to know more details, you can see my CV here. If you are interested in my motivation, you can also take a look at my SoP for application.
Work Email: yichuanjiaoda@sjtu.edu.cn
Personal Email: yichuanmistygrass@gmail.com
Education
Shanghai Jiao Tong University
Sept. 2020 -- June 2024
B.Eng. in Computer Science at ACM Honors Class, advised by Prof. Quan Chen, Prof. Yong Yu
New York University Courant Institute
July. 2023 -- Dec. 2023
Research assistant, advised by Prof. Jinyang Li
Publications
Optimizing Dynamic Neural Networks with Brainstorm pdf
Weihao Cui, Zhenhua Han, Lingji Ouyang, Yichuan Wang, Ningxin Zheng, Lingxiao Ma, Yuqing Yang, Fan Yang, Jilong Xue, Lili Qiu, Lidong Zhou, Quan Chen, Haisheng Tan, Minyi Guo.
OSDI 2023
DiskGNN: Bridging I/O Efficiency and Model Accuracy for Out-of-Core GNN Training pdf
Renjie Liu*, Yichuan Wang*, Xiao Yan, Zhenkun Cai, Minjie Wang, Haitian Jiang, Bo Tang, Jinyang Li
*indicates equal contribution
submitted VLDB 2025
Selected Projects
A system that can build its own scene and track the refraction and reflection of light in it. Several compilation-related optimizations were undertaken to enhance the overall performance.
Using the technology of ANTLR, semantic checking, code generation, and optimization to develop a compiler that compiles C-and-Java-like language to RV32I Assembly from scratch.
RISC-V CPU Implemented in Verilog RTL
Designed a RISC-V CPU with Write Buffer, ICache, DCache, and Branch Prediction. Supports RV32I instruction set (2.1-2.6 in RISC-V User Manual). Used Vivado to generate bitstream and program the Basys3 FPGA board.
Designed a train ticket system with multi-user support and privilege management. I implemented the backend and built a Bplustree storage. All used C++ STL data structures are from scratch (including map, and queue).