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Yichuan Wang

Bio 微信图片_20230814214647

I am a first-year PhD student at UC Berkeley in SkyLab and received my B.E. in Computer Science and Technology from ACM Honored Class, Shanghai Jiao Tong University(SJTU). I am interested in machine learning systems and high-performance computing systems particularly in distributed systems for large ML model training/serving and developing tailored abstractions for unique ML computational patterns to enhance performance. To be more specific, currently, I am more interested in LLM serving/scheduling, multi-agent systems, and GraphRAG. If you share similar interests, I'd love to chat.

Previously, I collaborated with Prof.Jinyang Li in NYU and Dr.Minjie Wang on a project related to scaling up GNN training. In SJTU, I am supervised by Prof. Quan Chen at EPCC. I like to communicate with different people, so you can feel free to contact me via email wechat:15858459091 or yichuanwang0324 or twitter If you are willing to know more details, you can see my CV here. If you are interested in my motivation, you can also look at my SoP for application.

In my spare time, I also contribute to open-source projects, like SGLang recently.

Work Email: yichuan_wang@berkeley.edu

Personal Email: yichuanmistygrass@gmail.com

Google Scholar image/svg+xml Google Scholar Google Scholar CV image/svg+xml CV CV

News

[08/29/2024] After being rejected once, DiskGNN has finally been accepted by SIGMOD25. See you in Berlin! ​😄

[08/13/2024] Starting my PhD journey at SkyLab—excited. 🎉

[05/08/2024] We put DiskGNN on Arxiv If you want to train a super-large-scale GNN while balancing speed and accuracy, you should try it! We will integrate it into DGL asap. 🔥

Education

UC Berkeley Image title

Starting from Sept. 2024

PhD in EECS

Shanghai Jiao Tong UniversityImage title

Sept. 2020 -- June 2024

B.Eng. in Computer Science at ACM Honors Class, advised by Prof. Quan Chen, Prof. Yong Yu

New York University Courant InstituteImage title

July. 2023 -- Dec. 2023

Research assistant, advised by Prof. Jinyang Li

Publications

Optimizing Dynamic Neural Networks with Brainstorm pdf

Weihao Cui, Zhenhua Han, Lingji Ouyang, Yichuan Wang, Ningxin Zheng, Lingxiao Ma, Yuqing Yang, Fan Yang, Jilong Xue, Lili Qiu, Lidong Zhou, Quan Chen, Haisheng Tan, Minyi Guo.

Accepted by OSDI 2023

DiskGNN: Bridging I/O Efficiency and Model Accuracy for Out-of-Core GNN Training pdf

Renjie Liu*, Yichuan Wang*, Xiao Yan, Zhenkun Cai, Minjie Wang, Haitian Jiang, Bo Tang, Jinyang Li

*indicates equal contribution

Accepted by SIGMOD 2025

Services

  • [08/2024] Eurosys'25 Artifact Evaluation Committee
  • [07/2024] SIGCOMM'24 Artifact Evaluation Committee
  • [04/2024] OSDI’24 Artifact Evaluation Committee
  • [04/2024] USENIX ATC’24 Artifact Evaluation Committee

Misc/Hobbies

I like playing basketball! (But unfortunately, it seems that there aren't any good basketball courts near Berkeley.) So now, I might (or rather, I can only) play more badminton(I still enjoy). Besides that, I've been an NBA fan for 15 years, and I like Chris Paul! In recent years, I've also become very interested in the Premier League(I love Manchester City, come on Blue Moon!). If you share the same interests, we should chat/hang out!

Selected Projects

RayTracer

A system that can build its own scene and track the refraction and reflection of light in it. Several compilation-related optimizations were undertaken to enhance the overall performance.

Compiler for Mx* Language

Using the technology of ANTLR, semantic checking, code generation, and optimization to develop a compiler that compiles C-and-Java-like language to RV32I Assembly from scratch.

RISC-V CPU Implemented in Verilog RTL

Designed a RISC-V CPU with Write Buffer, ICache, DCache, and Branch Prediction. Supports RV32I instruction set (2.1-2.6 in RISC-V User Manual). Used Vivado to generate bitstream and program the Basys3 FPGA board.

Ticket System

Designed a train ticket system with multi-user support and privilege management. I implemented the backend and built a Bplustree storage. All used C++ STL data structures are from scratch (including map, and queue).